Its a characteristic of SR flip-flops (and asynchronous S & R inputs to single stage clocked flip-flops) that they enter a state with both Q and /Q asserted if *BOTH* S and R are asserted. He's already been shown how to three months ago! (toggling)-a-signal-connection/ If toggling a logic signal with a ground referenced switch + good noise immunity are essential requirements, I favor the use of a dual D type flip-flop with non-inverted Set and Reset inputs. The other two channels can be used as inverters to implement Gnuarm's toggle lach suggestion. I don't know if you have any other use for logic gates, but the FF can use any inverting gate like NAND or NOR.īelzrebuth is only using one channel of the 4053 triple SPDT switch. Sometimes it is convenient to be able to use ground and a switch on the end of a wire can pick up noise which is not good on a high impedance input like a CMOS gate. Both of these circuits have the switch not tied to ground and one end connected directly to a gate input. I would make the lower resistor in the drawing a smaller value to make sure nothing odd changes if you hold the button pressed. Another circuit a bit further down the page uses two capacitors. Otherwise the CMOS devices may take some time to drain it. That will make sure the cap voltage is drained on power down. If you want to assure start up in this state even a short time after powering off, add a very large resistor, 1 M or more, in parallel with the cap. This circuit should start up with the capacitor leg of the inverters low and the other leg high (the output on the right inverter). See the illustration a short way down the page with the two inverters. You can do the same thing with a pair of inverters, nor or nand gates with two resistors and a capacitor. BTW, why the transistor FF? That circuit uses two transistors and ten passives. So you need a negative voltage on Vee? It can just be grounded if the signals on the analog pins don't go negative.
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